The present invention relates to a signal input circuit and, more particularly, to such a circuit having a CMOS inverter for receiving an input signal of g Transistor-Transistor-Logic (TTL) level.
As a signal input circuit, a CMOS inverter is usually employed in a logic circuit. The CMOS inverter has such a circuit construction as shown in FIG. 6, wherein a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2 are connected in series between first and second power supply terminals 3 and 4. The first power supply terminal 3 is applied with a power voltage of a VDD level and the second terminal 4 is applied with the ground level (GND). The gates of the transistors Q1 and Q2 are connected in common to an input terminal 1 and the connection point thereof is lead out as an output terminal 2.
When the input signal applied to the terminal 1 takes such a level that is equal to a logical threshold level of the inverter, the same current flows through both of the transistors Q1 and Q2, and each of them thus operates in a saturated region. Accordingly, the following equation (1) is derived: ##EQU1## wherein BP and BN indicate the current gains of the transistors Q1 and Q2, respectively, VTP and VTN indicating the threshold voltages thereof, respectively, VINV indicating the logical threshold level of the inverter, and VDD indicates the power voltage between the terminals 3 and 4. The equation (1) is rewritten as follows: ##EQU2##
Considering here that the CMOS inverter shown in FIG. 6 is used for an input circuit receiving a signal of the TTL level, this signal has an amplitude between 0.8. V to 2.0 V and therefore the threshold level VINV of the inverter is required to be designed to an intermediate level of the amplitude of the signal. Typically, the threshold level is designed to be 1.4 V. Assuming here that the power voltage VDD is 5 V, VINV =1.4 V, and VTN=VTP=0.7 V, the following equation (3) is derived from the equation (2) EQU BN/BP=17.14 (3)
Thus, by designing the current gains of the transistors Q1 and Q2 to satisfy the equation (3), the CMOS inverter shown in FIG. 6 operates as an input signal circuit for receiving a signal of the TTL level. Since the current gain of a MOS transistor is proportional to the gate width and is inversely proportional to the gate length, the ratio in current gain between the transistors Q1 and Q2 indicated above can be obtained from the gate width and/or length thereof. For example, the ratio of the gate width to the gate length of the transistor Q2 is designed about 17 times as large as the ratio of the gate width to the gate length of the transistor Q1.
Recently, due to a demand for low power voltage, the power supply voltage applied to the logic circuit has been decreased from 5 V to 3 V. That is, the logic circuit is required to operate on not only the 5 V power voltage but 3 V power voltage. However, the CMOS inverter composed of the transistors Q1 and Q2 having the respective current gains designed above hardly has a TTL comparative characteristics when the power voltage is lowered to 3 V.
More particularly, solving the equation (1) for the threshold voltage VINV, the following equation (4) is obtained: EQU VINV=(VDD-.vertline.VTP.vertline.+mVTN)/(1+m) (4)
wherein m=.sqroot.BN/BP.
Since VDD=3 V and BN/BP=17.14, the threshold voltage VINV becomes equal to 1.01 V. This threshold voltage exists within the amplitude of the TTL level signal, and hence the CMOS inveRter can receive the TTL level signal to produce a logic high or low level output signal in accordance therewith. However, if the threshold voltage of the transistor Q2 is changed to 0.4 V due to the temperature variation and/or manufacturing conditions, the logical threshold level of the inverter is changed to 0.77 V. The output signal from the inverter is thereby held at the low level irrespective of the level of the input signal.